1. Field of the Invention
This invention generally relates to complementary-metal-oxide-semiconductor (CMOS) circuitry and, more particularly, to a noise cancellation circuit to protect digital CMOS circuitry from high frequency noise on the power supply.
2. Description of the Related Art
Digital circuitry typically operates in conjunction with high-speed clock signals sourced from a crystal oscillator or phase-locked loop (PLL). Digital circuitry and the related clock distribution circuits normally use the same power supply. As a result, harmonic components over a wide range of frequencies of both the clock and the processed data signals can appear as noise on the power supply lines. Today's microprocessors work in the gigahertz frequency range, and such frequencies impose tight requirements in terms of clock skew and clock jitter to the microprocessor clock distribution, and the sensitivity of support circuitry to clock-related noise.
Simple passive low-pass filtering, e.g., a series resistor and shunt capacitor, is usually the only technique still employed by designers to cope with clock jitter generated by supply noise. The values of the resistor and capacitor can be tuned to optimize the filter response, and inductors can be added to attenuate particular frequencies. However, this approach is very expensive since significant active portions of an integrated circuit (IC) chip must be dedicated to the decoupling capacitors.
It would be advantageous if high-frequency noise on a power supply could be cancelled using an active circuit with a size factor that is less than a filtering capacitor.